A parameter of considerable interest to those testing networks and network equipment, as well as for other reasons, is packet latency. That is, how long it takes between a packet entering the network or network equipment at one point (the source) and when it is delivered at some other point (the destination).
Traditionally, packet latency has been measured by ensuring that the test equipment at the source and destination are equipped with synchronized clocks. Just as the test packet is submitted to the network at the source, the current time is encoded within that packet itself. When the packet is received at the destination, the time of arrival is noted, and by subtracting that from the time contained within the packet the latency can be calculated.
For this to work, the clocks of the source and destination test equipment must be synchronized. Synchronization has been achieved when the packets are originated and terminated in field-programmable gate arrays (FPGAs) with synchronized clocks. The synchronization consists of a central time source with a regular pulse signal to mark the start of each period (typically 10 times per second), a serial line to give the absolute time of the next pulse, and a higher frequency clock (typically 10 MHz) to maintain timing between pulses.
FIG. 1 is a high level schematic illustration of a conventional test system 10. The system 10 includes a clock distribution network at 12 coupled to a master clock 14 which generates a master clock reference 16. As shown, distribution network 12 supplies the same master clock reference 16 to interface logic 18 associated with individual FPGA-based test cards 20. Each test card 20 can include one or more test interfaces 22.
FIG. 2 is a more detailed view of the connection between interface logic 18 and its associated FPGA-based test card 20. Using master clock reference 16, interface logic 18 provides test card 20 with the following signals: clock 24, pulses 26 and timestamp 28. Clock 24 is typically a 10 MHz reference clock while pulses 26 is typically a 10 pulses per second tick. Timestamp 28 is typically provided along a serial line carrying the actual time of day corresponding to the next pulse. Timestamp 28 can be in, for example, ASCII text. For example, timestamp 28 may carry “2013-05-31-15-45-23.7” indicating that the next pulse will occur on 31 May 2013 at time 15:45 and 23.7 seconds. Between pulses, FPGA test card 20 can count clock cycles to get a time accurate to the clock period and can use this to determine the transmission and reception time of frames.
FPGAs are integrated circuits which are designed to be programmed by the user to provide a particular function. The function is therefore effectively provided in hardware. FPGAs provide a fast, powerful tool for the circuit designer. In contrast, the same function provided using a CPU (central processing unit) is effectively provided via software. While FPGAs are powerful, fast and very useful, they are much more expensive than CPU devices.